ddu8c doc #97013 data delay devices, inc. 1 1/28/97 3 mt. prospect ave. clifton, nj 07013 5-tap, hcmos-interfaced fixed delay line (series ddu8c) features packages five equally spaced outputs fits standard 8-pin dip socket low profile auto-insertable input & outputs fully cmos interfaced & buffered 10 t 2 l fan-out capability functional description the ddu8c-series device is a 5-tap digitally buffered delay line. the signal input (in) is reproduced at the outputs (t1-t5), shifted in time by an amount determined by the device dash number (see table). the total delay of the line is measured from in to t5. the nominal tap-to-tap delay increment is given by one-fifth of the total delay. series specifications minimum input pulse width: 40% of total delay output rise time: 8ns typical supply voltage: 5vdc 5% supply current: i ccl = 40 m a typical i cch = 10ma typical operating temperature: 0 to 70 c temp. coefficient of total delay: 300 ppm/ c 20% 20% 20% 20% 20% vdd gnd in t1 t2 t3 t4 t5 ddu8c functional diagram 1997 data delay devices data delay devices, inc. 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 in n/c n/c t2 n/c t4 gnd vdd n/c t1 n/c t3 n/c t5 8 7 6 5 1 2 3 4 in t2 t4 gnd vdd t1 t3 t5 ddu8c-xx dip ddu8c-xxa1 gull-wing ddu8c-xxb1 j-lead ddu8c-xxm military dip military smd ddu8c-xxmd1 ddu8c-xxmd4 pin descriptions in signal input t1-t5 tap outputs vdd +5 volts gnd ground dash number specifications part number total delay ( ns) delay per tap ( ns) ddu8c-5050 50 2.5 10.0 3.0 ddu8c-5060 60 3.0 12.0 3.0 ddu8c-5075 75 4.0 15.0 3.0 ddu8c-5100 100 5.0 20.0 3.0 ddu8c-5125 125 6.5 25.0 3.0 ddu8c-5150 150 7.5 30.0 3.0 ddu8c-5175 175 8.0 35.0 4.0 ddu8c-5200 200 10.0 40.0 4.0 ddu8c-5250 250 12.5 50.0 5.0 note: any dash number between 5004 and 5250 not shown is also available.
ddu8c doc #97013 data delay devices, inc. 2 1/28/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes high frequency response the ddu8c tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. however, for a given input condition, the deviation will be repeatable from pulse to pulse. contact technical support at data delay devices if your application requires device testing at a specific input condition. power supply bypassing the ddu8c relies on a stable power supply to produce repeatable delays within the stated tolerances. a 0.1uf capacitor from vdd to gnd, located as close as possible to the vdd pin, is recommended. a wide vdd trace and a clean ground plane should be used. device specifications table 1: absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 2: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min typ max units notes high level output voltage v oh 3.98 4.4 v v dd = 5.0, i oh = max v ih = min, v il = max low level output voltage v ol 0.15 0.26 v v dd = 5.0, i ol = max v ih = min, v il = max high level output current i oh -4.0 ma low level output current i ol 4.0 ma high level input voltage v ih 3.15 v low level input voltage v il 1.35 v input current i ih 0.10 m a v dd = 5.0
ddu8c doc #97013 data delay devices, inc. 3 1/28/97 3 mt. prospect ave. clifton, nj 07013 package dimensions .500 max. 1 2 3 4 5 6 7 8 .290 max. .015 typ. .070 max. .018 typ. .300 .010 3 equal spaces each .100 .010 non-accumulative .280 max. .350 max. .010 .002 lead material: nickel-iron alloy 42 tin plate ddu8c-xx (commercial dip) .180 typ. .500 max. 1 2 3 4 5 6 7 8 .290 max. .020 typ. .440 max. .300 typ. .010 typ. .300 typ. .020 typ. ddu8c-xxm (military dip) .520 max. 1 2 3 4 5 6 7 8 .430 typ. .020 typ. .040 typ. .100 .110 .300 .300 max. .270 typ. .010 typ. .050 typ. ddu8c-xxa1 (commercial gull-wing) .520 max. 1 2 3 4 5 6 7 8 .320 typ. .020 typ. .040 typ. .100 .110 .300 .350 max. .270 typ. .050 typ. .110 typ. ddu8c-xxb1 (commercial j-lead) .510 max. 1 7 8 .510 max. 14 .300 typ. .017 .050 .100 .100 .300 .300 .008 .045 .025 .360 typ. .065 typ. .065 typ. ddu8c-xxd1 (commercial smd) ddu8c-xxmd1 (military smd) .200 max. ( com) .225 max. (mil) .080 .080 .510 max. 1 7 8 14 .510 max. .017 .050 .300 typ. .100 .100 .650 .008 .005 .065 typ. .360 typ. .065 typ. ddu8c-xxd4 (commercial smd) ddu8c-xxmd4 (military smd) .200 max. ( com) .225 max. (mil)
ddu8c doc #97013 data delay devices, inc. 4 1/28/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 1 fast-ttl gate supply voltage (vdd): 5.0v 0.1v c load : 5pf 10% input pulse: high = 5.0v 0.1v threshold: 2.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 5.0 ns max. (measured between 0. 5v and 4.5v ) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the de vice. t1 out trig in ref trig test setup device under test (dut) time interval counter pulse generator computer system printer in t2 t3 t4 t5 0.5v 0.5v timing diagram for testing t rise t fall per in pw in t rise t fall 2.5v 2.5v 4.5v 4.5v 2.5v 2.5v v ih v il v oh v ol input signal output signal
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